CPU loop + L1 access: 1.31 ns = 2 cy ( delay: 33.82 ns = 51 cy ) caches: level size linesize miss-latency replace-time 1 8 KB 32 bytes 16.00 ns = 24 cy 10.44 ns = 16 cy 2 256 KB 128 bytes 198.83 ns = 298 cy 150.75 ns = 226 cy TLBs: level #entries pagesize miss-latency 1 64 4 KB 36.09 ns = 54 cy